1. Field of the Invention
The present invention relates to an integrated memory control apparatus. More particularly, the present invention relates to an integrated memory control apparatus for a serial transmission interface.
2. Description of Related Art
Flash memories are commonly used components on main boards of the computers, and are widely applied in personal computers and notebook computers. Various kinds of data may be stored in the flash memory, and therefore South Bridge chips and various kinds application specific integrated circuits (ASICs) disposed on the main board may complete specific instructions by accessing data stored in the flash memory.
FIG. 1 is a block diagram illustrating a part of a conventional main board. Referring to FIG. 1, the conventional main board 100 includes flash memories 110 and 120, a South Bridge chip 130 and an ASIC 140. The ASIC 140 includes a micro-processor unit 141 and a memory controller 142. The South Bridge chip 130 and the ASIC 140 may respectively access the data stored in the flash memories 110 and 120 through the serial peripheral interfaces (SPI) SPI1 and SPI2.
Moreover, the memory controller 142 is used for controlling read and write of the flash memory 120. The micro-processor unit 141 is used for writing the data into the flash memory 120 or reading the data from the flash memory 120 according to an operation of the memory controller 142. During a data transmission, the data transmission between the micro-processor unit 141 and the flash memory 120 is performed via a general transmission interface GTI1. Since the memory controller 142 may transmit a waiting signal to the micro-processor unit 141 through a signal line of the general transmission interface GTI1, the micro-processor unit 141 may timely stop reading of the data from the flash memory 120 in response to the received waiting signal.
However, as to the South Bridge chip 130, the signal line within the serial peripheral interface SPI1 cannot transmit the waiting signal. Therefore, when the South Bridge chip 130 begins to read the data from the flash memory 110 by sending a request signal, a wait state cannot be arbitrarily inserted during data reading of the South Bridge chip 130. In other words, the South Bridge chip 130 and the micro-processor unit 141 of the ASIC 140 cannot share the same flash memory. In this case, fabrication cost of the conventional main board 100 is greatly increased, and a layout area of its printed circuit board will be more complicated, and accordingly, it is highly desirable to simplify and improve the circuit layout of the main board.